The majority of present day integrated circuits (ICs) are implemented by using a plurality of interconnected field effect transistors (FETs), also called metal oxide semiconductor field effect transistors (MOSFETs), or simply MOS transistors. An MOS transistor includes a gate electrode as a control electrode formed over a semiconductive substrate, and spaced apart source and drain electrodes within the substrate between which a current can flow. A control voltage applied to the gate electrode controls the flow of current through a channel in the semiconductive substrate between the source and drain electrodes.
A continuing trend in the semiconductor industry is to manufacture ICs with higher device densities by scaling down dimensions (e.g., at submicron levels) on semiconductor wafers. To accomplish such high densities, smaller feature sizes, smaller separations between features and layers, and/or more precise feature shapes are required, such as metal interconnects or leads, for example. The scaling-down of integrated circuit dimensions can facilitate faster circuit performance and/or switching speeds, and can lead to higher effective yield in IC fabrication processes by providing or “packing” more circuits on a semiconductor die and/or more die per semiconductor wafer, for example.
One way to increase packing densities is to decrease the thickness of transistor gate dielectrics to shrink the overall dimensions of transistors used in ICs and electronic devices. Transistor gate dielectrics (e.g., silicon dioxide or nitrided silicon dioxide) have recently been reduced considerably to reduce transistor sizes and facilitate improved performance. Thinning gate dielectrics can have certain drawbacks, however. In one example, a polycrystalline silicon (“polysilicon”) gate overlies a thin gate dielectric, and polysilicon naturally includes a depletion region where it interfaces with the gate dielectric. As used herein, the term “overlie” refers to a layer or device that is formed vertically above another layer or device (possibly with one or more intervening layers or devices) when the integrated circuit device is oriented as depicted in the figures. This depletion region can provide an insulative effect rather than conductive behavior, which is desired of the polysilicon gate since the gate is to act as an electrode for the transistor.
By way of example, if the depletion region acts like a 0.8 nm thick insulator and the gate dielectric is 10-nm thick, then the depletion region effectively increases the overall insulation between the gate and an underlying transistor channel by eight percent (e.g., from 10 nm to 10.8 nm). It can be appreciated that as the thickness of gate dielectrics are reduced, the effect of the depletion region can have a greater impact on dielectric behavior. For example, if the thickness of the gate dielectric is reduced to 2 nm, the depletion region would effectively increase the gate insulator by about 40 percent (e.g., from 2 nm to 2.8 nm). This increased percentage significantly reduces the benefits otherwise provided by thinner gate dielectrics.
Metal gates can be used to mitigate adverse effects associated with the depletion region phenomenon because, unlike polysilicon, little to no depletion region manifests in metal. Metal gates were commonly used prior to the more recent use of polysilicon gates. An inherent limitation of such metal gates, however, led to the use of polysilicon gates. In particular, the use of a single work function metal proved to be a limitation in high performance circuits that require dual work function electrodes for low power consumption. The work function is the energy required to move an electron from the Fermi level to the vacuum level. In modern complementary MOS (“CMOS”) circuits, for example, both p-channel MOS transistor devices (“PMOS”) and n-channel MOS transistor devices (“NMOS”) are generally used, where a PMOS transistor requires a work function on the order of 5 eV and an NMOS transistor requires a work function on the order of 4 eV. A single metal may not be found, however, which can produce a metal gate that provides such different work functions. Polysilicon gates are suited for application in CMOS devices since some of the gates can be substitutionally doped in a first manner to achieve the desired work function for PMOS transistors and other gates can be substitutionally doped in a second manner to achieve the desired work function for NMOS transistors. However, polysilicon gates suffer from the aforementioned gate depletion.
Fully silicided (FUSI) gates eliminate the problem of polysilicon depletion. FUSI gates also reduce the gate conductance that can further improve device performance. In the prior art, a FUSI gate is conventionally formed by depositing a metal layer (such as Ni, Ti, Co, etc.) over an exposed polysilicon gate region, pre-annealing to provide the required diffusion, removing the unreacted metal, and then annealing the semiconductor structure to form a more stable silicide phase. The deposited metal reacts with the exposed polysilicon gate to transform the polysilicon gate fully into a silicided gate. FUSI gates normally have a work function near the middle of the silicon band structure. However, CMOS devices normally require a conductive gate with a work function near the band edge; i.e., near the conduction band for an NMOS device and near the valence band for a PMOS device, respectively. Thus, for CMOS technologies with FUSI gates, the different work functions required for each of the NMOS and PMOS portions of the CMOS device may also need to be provided by the inclusion of various work-function modifying materials (such as work-function modifying metals) into the gate stack.
In addition, the doped silicide gate electrodes of the MOS devices are typically formed to be much thicker than the depth of the silicide formed in the source/drain (S/D) regions. Because of these differing thicknesses, the gate silicidation is usually formed separate from the S/D silicidation, typically separated by a complex and costly CMP process. If the gate silicide and the S/D silicide were formed during the same silicidation process using convention approaches, the silicide thickness in the S/D region would far exceed the desired amount, leading to possible defects. That is, with increasing the amount of silicidation of the gate electrode to a FUSI gate electrode, S/D areas cannot be silicided independent of the gate electrode, and if done simultaneously, would tend to “pipe,” which is a defect mechanism wherein silicide creeps into the channel region under the gate electrode, or simply breaks through the depletion zone between body and S/D area, if too much silicidation is supplied to the S/D regions.
Accordingly, it is desirable to provide improved methods for fabricating integrated circuits using CMOS technologies. Additionally, it is desirable to be able to form a fully silicided gate of a CMOS transistor using a simple and cost effective process that may be employed in the fabrication of high density CMOS devices. Furthermore, other desirable features and characteristics of the present disclosure will become apparent from the subsequent detailed description and the appended claims, taken in conjunction with the accompanying drawings and the foregoing technical field and background.